NePSim - A Network Processor Simulator with Power Evaluation Framework by Yan Luo, Jun Yang, Laxmi N. Bhuyan and Li Zhao, University of California Riverside

    The NP research community needs an integrated infrastructure that provides the maximum flexibility in simulating different architecture extensions of a network processor and provides detailed power dissipation analysis accurately and efficiently. We present NePSim, an integrated system that includes a cycle-accurate architecture simulator, an automatic formal verification engine, and a parameterizable power estimator of a network processor that consists of clusters of multi-threaded execution cores, memory controllers, input/output ports, packet buffers and high speed buses. The simulator supports the IXP1200 microengine ISA and performs an execution-driven simulation that reproduces IXP's internal operation. A comprehensive set of statistics is collected and reported at the end of execution to facilitate performance analysis. The verification engine, called iveri, can validate the simulation from the execution log traces using user-defined constraints in a verification language. The power estimator combines a suite of models (XCacti, Wattch, and Orion) for dynamic power measurements and calculates results based on per-cycle resource usage counts.

    We ported four representative NP applications to conduct the experiments: IP forwarding (ipfwdr), URL routing (url), MD4 and network address translation (nat). To verify NePSim against IXP1200, we ran four benchmarks and measured the performances in terms of throughput (Mbps, megabits per second) and average packet processing time (cycles). We observed an average error of %1 in throughput and 6% in average processing time across the four benchmarks compared to the SDK simulator supplied by Intel.

    With NePSim, we conduct a set of experiments as follows:

• We study the impact of having more number of MEs on the total packet throughput measured in Mbps (megabits per second) and the ME idle time due to memory contention. Intuitively, the throughput of a benchmark should increase with the number of MEs or threads. However, for memory intensive benchmarks (url and md4), increasing the number of threads means increasing the memory contention since the memories are shared among all threads. When a program is memory bound, it often happens that all the threads in an ME are swapped out of pipeline waiting for their memory references, resulting an idle ME. The abundant core idle time gives us power-saving opportunities.

• We develop a model for power consumption of the IXP1200 and the MEs. In particular, we identify those components where bulk of the power is spent. It is interesting to see from the result that the ALU takes most power (45% on average), followed by the control store (28%) where the program is stored. This is because the control store is accessed almost every cycle.  The third power hungry component is the general purpose register (GPR) files (13%), where instruction operands and results are stored. Even when data are loaded from the memory the transfer files, they are moved again to GPRs for ALU operations.

• We apply Dynamic Voltage Scaling (DVS) technique to reduce ME power consumption. The average ME idle time is shown to be abundant (one average 10-23%) since most of the benchmarks are memory bound. Applying DVS while MEs are not very active can reduce the total power consumption substantially. Our scheme observes the ME idle time periodically. Once the percentage of the idle time in the past period is over a threshold, we scale down the voltage and frequency (VF in short) by one step unless the minimum allowable VF is hit. If the percentage is below threshold, indicating that the ME in the past period is relatively busy, we scale up the VF by one step unless they are at maximum allowable values. Overall, we achieve maximum 17% of power savings of the NP over four network applications with less than 6% performance loss.

    NePSim has drawn a lot of attention from both the academic community and the industry. Since July 2004 to the date of this paper, NePSim has over 100 downloads worldwide. We welcome feedback from users, and we are currently extending NePSim to simulate IXP2400/2800 network processors.  The source code of the complete simulator can be downloaded from http://www.cs.ucr.edu/~yluo/nepsim/.

References

[1] Yan Luo, Jun Yang, Laxmi N. Bhuyan, Li Zhao, "NePSim: A Network Processor Simulator with Power Evaluation Framework," IEEE MICRO Special Issue on Network Processors for Future High-End Systems and Applications, Sept/Oct 2004.

[2] Xi Chen, Yan Luo, Harry Hsieh, Laxmi Bhuyan, F. Balarin, "Utilizing Formal Assertions for System Design of Network Processors, " Design Forum, Design Automation and Test in Europe (DATE), 2004.